1. Field of the Invention
The present invention relates to a packet switching system, particularly to a header driven type packet switching system adapted for a high-speed packet switching node (non-x.25 protocol base) in an ISDN (integrated services digital network) and in a packet network.
To cope with recent high-speed communications, there is an increasing demand for packet type digital data communications, and therefore, a header driven type packet switching system which exchanges packets according to packet headers by hardware autonomous line switches, has been put to practical use to improve the packet switching processing capacity and processing speed.
2. Description of the Related Art
The basic functions required for the header driven type packet switching system are a routing function, for decoding the header of an input packet for transfer to a destination, and a function for rewriting the header with the virtual call number of a selected line.
Such a prior art header driven type packet switching system is disclosed, for example, in Japanese Unexamined Patent Publication No. 61-127250.
In a conventional header driven type packet switching, header processing circuits, each of which decodes the header of an input packet, rewrites the information in the header, and transmits a control signal to a switching portion to select an outgoing line for the packet, are provided only in a fixed correspondence with incoming lines of the switching system.
Therefore, when a plurality of packets are continuously transmitted through a particular incoming line, the first packet must be completely processed before the next packet can be processed, and thus the processing of the following packets may be greatly delayed, or those packets may have to be dropped.
To solve the above problems in the prior art, the inventors of the present invention presented, prior to the present invention, a new header driven packet switching system and method in which, by providing header processing circuits arranged independently of the incoming lines, successive data packets can be efficiently and flexibly processed without overlong delay, which was filed as Japanese patent application Ser. No. 62-36736, on Feb. 19, 1987.
The above-mentioned preceding system (herein after referred to as the preceding system) will be later described in more detail with reference to the drawings.
The above-mentioned preceding header driven type packet switching system can achieve a hardware autonomous control without software for the switches for each packet, to realize a packet switching process which can cope with a large scale data packet. Nevertheless, this system has the following drawbacks:
.circle.1 the processing speed of LSIs used in the packet processing circuits and in the switching mechanisms are limited when the number of incoming and outgoing lines is increased; and
.circle.2 when a transmission capacity (incoming lines and the number of calls are increased, a capacity of the memory for holding the next virtual call number and the outgoing line number in each packet header processing circuit PH must be increased.